Trench DMOS transistors are widely used in integrated circuits for power transistors. The gate electrode is a conductive material, which located in a trench in the transistor substrate, where the sidewalls and bottom of the trench are insulated with silicon dioxide.
In a typical discrete trench DMOS circuit, several trench DMOS transistors are fabricated in parallel. Therefore, on a typical discrete trench DMOS semiconductor, the trench DMOS devices share a common drain contact (the substrate), their sources are all shorted together with metal, and their gates are shorted together with polysilicon. It is often physically constructed using an array or matrix of smaller transistors all connected in parallel. For a discrete trench DMOS semiconductor, it is desirable to maximize the conductivity per unit area of trench DMOS transistor array when it is turned "on" by the gate.
In order to increase the density of the trench DMOS devices on a chip, it is desirable to minimize the contact size so that adjacent neighboring transistors (trenches) can be fabricated as closely as possible to each trench DMOS transistor pair. However, each masking step requires a mask alignment and therefore results in a possible alignment error, undesirably reducing yield. Expected mask alignment errors can be factored into the device dimensions in order to minimize the adverse affect on yield, but this approach increases the cell dimensions, thereby reducing the density of the trench DMOS transistors on the semiconductor and correspondingly decreasing the conductivity per unit area.
FIGS. 4A-4C schematically show the process flow in forming non-self-aligned contacts of trench DMOS in the prior art. FIG. 4A shows a pair of closely packed trenches 20 and 21 in semiconductor substrate 10. The trench 20 and trench 21 are substantially the same. Inside the trenches 20 and 21, an underlying dielectric layer 31 and a polycrystalline silicon plug 15 are deposited. An (ILD) layer 42 is then deposited over the surface of the semiconductor substrate 10 and trenches 20,21. The ILD layer 42 can be formed by a low temperature oxidation process with material of silicon oxide, tetraethylanthosilicate phospsilicate glass boronophosilicate glass or any combination of above. Then a photolithographic photoresist layer 17 is applied to form contact patterns. After that, as shown in FIG. 4C, ILD layer 42 is etched to expose contact regions 18a to 18c, and a plurality of ILD islands (noted as 32a-32d) stay on semiconductor surface and trenches 20,21.
After stripping off the photoresist layer 17, a conductive metal layer 19 is deposited to cover the ILD islands 32a-32d and those exposed contact regions 18a-18c. However, as mentioned above, the spacing 101 between trench 20 and trench 21 should be designed larger than the necessary contact size in order to compensate for the possible alignment error. Thereby, it is impossible to get the most closely packed devices (trenches 20 and 21) in the prior art process described above.
Since it is generally desirable to reduce the costs of manufacturing trench DMOS devices, it would be desirable to design devices as closely packed as possible. Therefore, under the same condition of the photolithographic resolution and alignment capability, it is desirable to eliminate the ILD islands (32a and 32b) on top of trench 20 and trench 21, respectively, in order to design the smallest spacing 101 between the trench edges of trench 20 and 21.